The present invention relates to a dynamic random access memory (DRAM) for image processing and, particularly, to a DRAM of this kind having high speed image processing performance.
A DRAM of this kind which is disposed between a CPU and a data display device of a compact computer such as EWS or personal computer for performing read/write of data to be displayed under control of the CPU has been widely used under the name of video RAM (VRAM) or graphic memory. The operating speed and flexibility in processing an image required for such memory is being increased more and more. In response to such requirements, a write per bit function for random write, a block write function for write in an assigned cell block having a plurality of bits (32 or 64) by 1 cycle clock pulse and/or a flush write function for write cells corresponding to an assigned number of rows (8 or 16 rows) by 1 cycle is attached to a VRAM as disclosed in U.S. Pat. No. 4,633,441.
However, when a control circuit for a laser printer is constructed with such VRAM, formation of graphic image and/or its modification must be performed by reading pixel data stored in an address of the VRAM, logically operating on it with new pixel data and/or display condition, forming pixel data after the modification and rewriting it in the same address. That is, it requires VRAM access operation and CPU operation over a plurality of clock pulse cycles for formation and/or modification of graphic image. Among logical operations, OR operation is most frequently used in the control circuit of the laser printer and a result of the OR operations is rewritten in the VRAM. In such a case, it requires at least 3 clock pulse cycles for an operation time for read/logical operation/rewrite, corresponding to at least 3 clock pulse cycles including access times to the CPU and the VRAM.
In order to reduce this time, U.S. Pat. No. 4,951,251 proposes a VRAM having an internal circuit formed within a semiconductor chip forming the VRAM, in which a level of a predetermined control signal supplied to the semiconductor chip prior to a chip selection signal is determined, a signal supplied to an address terminal in synchronism with the chip selection signal is taken in as a function signal and performs various operations including the logical operation function in response to the function signal. That is, the internal circuit includes a logical operation circuit which logically operates a read output from a RAM with a write signal from an external terminal in response to the function signal and generates a rewrite signal therefrom. In case where the logical operation performed in response to the function signal is an OR operation to form a logical sum (OR), the read output from a certain address of the RAM is OR operated with an input image data according to a read-modify-write operation and an OR output thereof is rewritten in the same address as new pixel data. This operation is completed within 1 clock pulse cycle. However, the read-modify-write operation requires a longer time compared with a simple write operation due to inclusion of read operation. For example, a usual write operation cycle time of such VRAM is 190 nS while the read-modify-write operation cycle time is 260 nS indicating an increase of about 37%.
Further, the internal circuit requires a function setting circuit for generating a function signal enabling the aforementioned logical operation as well as other logical operations, operation circuits for performing these logical operations and latch circuits for storing RAM read outputs, etc., causing the cost of VRAM to be increased.